A field effect transistor (FET) is a device in which regions called a source and a drain are provided in a semiconductor, in which each of the regions is provided with an electrode, potentials are supplied to the electrodes, and an electric field is applied to the semiconductor with the use of an electrode called a gate through an insulating film or a Schottky barrier so that the state of the semiconductor is controlled, whereby current flowing between the source and the drain is controlled. As the semiconductor, Group IV elements (Group 14 elements) such as silicon and germanium, Group III-V compounds such as gallium arsenide, indium phosphide, and gallium nitride, Group II-VI compounds such as zinc sulfide and cadmium telluride, and the like can be given.
In recent years, FETs in which an oxide such as zinc oxide or an indium gallium zinc oxide-based compound is used as a semiconductor have been reported (Patent Document 1 and Patent Document 2). In an FET including such an oxide semiconductor, relatively high mobility can be obtained, and such a material has a wide bandgap of greater than or equal to 3 electron volts; therefore, application of the FET including an oxide semiconductor to displays, power devices, and the like is discussed.
The fact that the bandgap of such a material is greater than or equal to 3 electron volts means that the material transmits visible light, for example; thus, in the case where the material is used in a display, even an FET portion can transmit light and the aperture ratio is expected to be improved.
Further, such a wide bandgap is common to silicon carbide, which is used in power devices; therefore, the oxide semiconductor is also expected to be applied to a power device.
Furthermore, a wide bandgap means few thermally excited carriers. For example, silicon has a bandgap of 1.1 electron volts at room temperature and thus thermally excited carriers exist therein at approximately 1011/cm3, while in a semiconductor with a bandgap of 3.2 electron volts, thermally excited carriers exist at approximately 10−7/cm3 according to calculation.
In the case of silicon, carriers generated by thermal excitation exist as described above even in silicon including no impurities, and thus the resistivity of the silicon cannot be higher than or equal to 105 Ωcm. In contrast, in the case of the semiconductor with a bandgap of 3.2 electron volts, a resistivity of higher than or equal to 1020 Ωcm can be obtained in theory. When an FET is manufactured using such a semiconductor and its high resistivity in an off state (a state where the potential of a gate is the same as the potential of a source) is utilized, it is expected that electric charge can be retained semipermanently.
Meanwhile, there are few reports on an oxide semiconductor which includes zinc or indium in particular and has p-type conductivity. Accordingly, an FET using a PN junction like an FET of silicon has not been reported, and a conductor-semiconductor junction as disclosed in Patent Document 1 and Patent Document 2, where a conductor electrode is in contact with an n-type oxide semiconductor, has been used for forming a source or a drain.
Note that in general academic books about semiconductors, the “conductor-semiconductor junction” is expressed as a “metal-semiconductor junction.” In this case, metal means a conductor. For example, a semiconductor which is doped at a high concentration and whose resistivity is significantly lowered, metal nitrides such as titanium nitride and tungsten nitride, metal oxides such as indium tin oxide and aluminum zinc oxide, and the like are also regarded as metal in “metal-semiconductor junctions.” However, the term “metal” might generally cause misunderstanding; therefore, the term “conductor-semiconductor junction” is used instead of the term “metal-semiconductor junction” in this specification.
For example, Patent Document 1 discloses an FET like the one illustrated in FIG. 5A, that is, an FET in which a first conductor electrode 103a called a source electrode and a second conductor electrode 103b called a drain electrode are provided in contact with one surface of a semiconductor layer 102 and a gate 105 is provided on the other surface side of the semiconductor layer 102 with a gate insulating film 104 interposed therebetween. Conductors are used for the first conductor electrode 103a, the second conductor electrode 103b, and the gate 105.
The gate 105 needs to have a portion overlapping with the first conductor electrode 103a and a portion overlapping with the second conductor electrode 103b, as shown by a width c in FIG. 5A. In other words, it is necessary in Patent Document 1 that c is larger than zero.
In an FET where a source electrode and a drain electrode are formed with the use of a conductor-semiconductor junction, when the carrier concentration of the semiconductor is high, current (off-state current) flows between the source electrode and the drain electrode even in an off state. Thus, the off-state current needs to be reduced by lowering the concentration of a donor or an acceptor in the semiconductor so that an i-type semiconductor (in this specification, an i-type semiconductor is a semiconductor whose carrier concentration derived from a donor or an acceptor is lower than or equal to 1012/cm3) is obtained.
Note that a concentration of a donor (or an acceptor) in this specification is a concentration of an element, a chemical group, or the like which could be a donor (or an acceptor) multiplied by an ionization rate thereof. For example, in the case where a donor element is included at 2% and the ionization rate thereof is 0.005%, the donor concentration is 1 ppm (=0.02×0.00005).
By the way, in a semiconductor circuit including an FET, especially in a semiconductor circuit in which either a p-channel FET or an n-channel FET can be used, an inverter which is one of fundamental circuits has a structure in which a resistor is connected in series with an FET as illustrated in FIG. 6A.
Alternatively, in some cases, the inverter may have a structure in which two FETs are connected in series and a short circuit between a drain and a gate of one of the FETs (typically, the one on the VH side) is caused so that a diode is formed, as illustrated in FIG. 6B. However, the inverter of FIG. 6B has a disadvantage in that a contact at a portion expressed by X in the drawing needs to be made in order to cause the short circuit between the drain and the gate of the FET and thereby high integration cannot be achieved.
In the inverter of the type of FIG. 6A, under the assumption that the resistance when the FET is on is RON and the resistance when the FET is off is ROFF, a resistor having a resistance value R which satisfies the relation, RON<<R<<ROFF, is connected to the FET. Here, it is preferable that R is higher than 10RON and lower than ROFF/10, and further preferable that R is higher than 100RON and lower than ROFF/100.
In this type of inverter, if the input is High, a current flows through the resistor and the on-state FET. At this time, the resistance between the VH and the VL in the inverter is R+RON. If the relation, R>>RON, is satisfied, the resistance of the inverter can approximate to R. Accordingly, when the power supply voltage of the inverter is assumed to be Vdd, power consumption can be expressed as Vdd2/R. Further, the output voltage can approximate to zero.
Even if the input is Low, a current flows through the resistor and the FET. At this time, the resistance of the inverter is R+ROFF. If the relation, R<<ROFF, is satisfied, the resistance of the inverter can approximate to ROFF. Accordingly, power consumption of the inverter can be expressed as Vdd2/ROFF. Further, the output voltage can approximate to Vdd.
As is apparent from the above relations, when R and ROFF are large values, power consumption can be reduced. In addition, in terms of the output voltage, it is preferable that R has an intermediate value between RON and ROFF, and it is ideal that R is (RON×ROFF)1/2. Accordingly, it is preferable that ROFF/RON is a large value.
Among conventional semiconductor circuits, a circuit including an amorphous silicon FET is known as such a semiconductor circuit in which either a p-channel FET or an n-channel FET can be used.
In an inverter circuit including an amorphous silicon FET, n-type amorphous silicon is used for a resistor. The n-type amorphous silicon is used as a material of a source and a drain of an FET and part of the amorphous silicon is processed so as to be used as a resistor. Since the n-type amorphous silicon does not have a high resistivity, the size of the resistor is larger than that of the FET.
By the way, an FET in which the carrier concentration is reduced by using an intrinsic (i-type) semiconductor having a band gap of 2 electron volts or more has an extremely small off-state current, that is, an extremely high ROFF and also has a mobility that is significantly high as compared to that of amorphous silicon, that is, a low RON; thus, the value of ROFF/RON is larger than or equal to 1010. With such a large value of ROFF/RON, the margin in forming or designing a resistor is increased.
However, in the FETs in which a conductor is directly in contact with a semiconductor as in Patent Document 1 and Patent Document 2, a material appropriate for a resistor cannot be found, unlike the case of the FET including amorphous silicon. In particular, an i-type semiconductor formed through reduction of the carrier concentration is considered as having an extremely high resistivity; therefore, usage of the i-type semiconductor for a resistor has not been assumed at all.
[REFERENCE]
[Patent Document]
    [Patent Document 1] United States Published Patent Application No. 2005/0199879    [Patent Document 2] United States Published Patent Application No. 2007/0194379